Take line monitoring to the next level with Die-to-Database Pattern Monitor. Tap the full potential of SEM images in ways that redefine production line monitoring for advanced technology nodes. Build the first of its kind 'Printed Pattern Database' and leverage that infrastructure to enable vast new opportunities for line monitoring and yield enhancement.

Intelligently decompose a full chip layout to generate a Design Decomposition Database. Rank the process marginality of all patterns of interest using a variety of empirical, statistical, and simulation techniques. Apply risk scores to bias care areas, review sampling, and more. Compare two or more layouts to identify similarities and differences, and proactively assess risk areas of new tape-outs.

Leverage the power of D2DB-PM and PCYM to generate and apply automated machine learning models that learn from real silicon data to make full-chip pattern risk assessments. Risk assessments can made to the patterns of most layers at most process steps.

Leverage the power of die-to-database to generate Bossung curves for any number of patterns. Comprehensively study patterning behavior across modulations to establish effective process windows.

Apply cutting edge patch image processing and machine learning techniques to create robust review sample plans for SEM Review that can optionally leverage the PCYM risk-scored pattern database.

Create your own custom solutions by integrating Anchor's powerful and vendor-neutral image processing technology for contour extraction, alignment, search, and defect detection. Image Explorer provides a toolkit of functions that empower you to create elaborate solutions for your unique applications.

I2DC (Image to Design Contour) is a specialized tool for the OPC / Lithography engineer who needs to compare simulation with real silicon to analyze the OPC workflow and perform adjustments as needed. It provides powerful image processing features to help engineers identify the design intent. And advanced tools such as multi-layer handling and image stitching enable shot level analysis.

Benefit from the collective experience of multiple teams in the fab by building a central defective pattern library and using it for pattern search, care area generation, risk analysis of new devices, comparison to OPC-simulated weak points, correlation with electrical fault analysis results, and other use cases.

NanoScope PRV is a model-based, pattern-centric full chip Post-RET/OPC verification software solution. It is a production-proven, distributed-computing application providing accurate lithography process modeling, comprehensive defect detection and analysis, and process window limiting pattern extraction.